1. Field of Invention
This invention relates to electrical testing of chip packaging assemblies and more particularly to buckling beam testing apparatus and methods of using such apparatus.
2. Background Information
Designers of today's computers continually seek to develop products having increased operating speed and reduced size. The desire for more speed in less space has required that larger and larger numbers of electrical circuits be packed into smaller and smaller volumes. The resulting increase in circuit density, however, has given rise to substantial difficulty in testing such assemblies.
To achieve increased circuit density, designers have resorted to techniques that shrink the number and size of the interconnections between circuits, and between the circuits and the outside world. These techniques, referred to generally as Very Large Scale Integration (VLSI), include grouping as many as 100 integrated circuit chips on a multilayer ceramic (MLC) substrate as small as 90 mm square to form densely packed circuit assemblies. The MLC substrate features multiple layers of alternating metalization and ceramic insulation which together make up the interconnections. These interconnections electrically couple the chips and facilitate transmission of input and output signals and power to and from the chips. Use of metal film technology permits the interconnections to be reduced in size and packed closely together. The ceramic insulation between and among metalization layers assures required electrical isolation.
Densely packing the circuits into a single assembly, however, causes both the cost and operating importance of the assembly to increase dramatically. It is, therefore, essential to manufacturing cost efficiency and system reliability that the MLC substrate be thoroughly tested before use. Pre-assembly testing screens out substrates having circuit defects that could render an assembly and its associated chips inoperative.
But, due to the nature of MLC, testing can present substantial problems. Particularly, it becomes difficult to accurately contact the dense MLC metalization patterns, and to test the large number of circuits in commercially acceptable times. Further, contacting problems are aggravated by metalization distortions and substrate height variations that arise during the MLC manufacturing process.
As noted, an MLC metalization pattern, in some cases, can accommodate up to 100 semiconductor chips. As more fully described in U.S. Pat. No. 4,245,273, issued Jan. 13, 1981 to I. Feinberg et al., and assigned to the assignee of this application, the MLC substrate features an upper surface, referred to as the "chip surface", having a dense metalization pattern that includes a multiplicity of chip mounting cites surrounded by engineering change pads (EC pads). Semiconductor chips are electrically and mechanically joined to the substrate at the mounting sites, while selective linking of the EC pads with discrete ribbon segments finalizes the chip interconnect patterns provided in the substrate. Such patterns can have in excess of 12,000 points that require contact for testing.
The lower surface of the MLC, while having far fewer metalization points requiring contact, nonetheless, also features a dense metalization pattern. The lower surface is designed to provide input and output signals and power to and from the chips, and, accordingly, is commonly referred to as the "I/O surface". The I/O surface metalization can have 1,800 or more metalization points which are interconnected by circuits throughout the substrate body with the chip cites and EC pads.
Contacting this profusion of points at the substrate chip and I/O surfaces is made more difficult by distortions that arise in the substrate during its manufacture. In the course of making the MLC, alternating layers of metalization and "green"; i.e., uncured, ceramic are stacked to form the substrate. This structure is subsequently fired at high temperature to cure the ceramic. During the curing process, the ceramic shrinks, nonuniformly, to produce a substrate that is "pillow" shaped; i.e., thicker at the middle than at the sides, and gathered at the corners. This distortion, which varies from substrate to substrate, results from the concentration of metalization at the structure's central region. Where less metal is present; e.g., the substrate sides and corners, the shrinkage is greater.
Because the metalization pattern is dense and nonuniformly distorted, and the substrate height uneven, contacting the substrate for test purposes presents a number of problems. Early test strategy included attempts to minimize the effects of height variations by testing with a few accurately placed probes arranged to span only a small region of the surface at a time. The probes were repeatedly applied to the substrate in a series of steps until the entire pattern was covered. However, excess amounts of time were required to complete this "step and repeat" process, and, as a result, it proved commercially unsuited for the more densely metalized substrates that have evolved. Additionally, the step and repeat process requires allowance for nonuniform distortion that arises over the substrate surface; a requirement that is difficult, at best, to meet.
Alternatively, the process of applying multiple probes configured to embrace the entire substrate metalization pattern in a single step was developed in an effort to speed testing. However, this too is problematic. For example, accurate alignment of multiple probes with an entire surface metalization pattern is difficult, and becomes more complicated where the pattern is nonuniformly and uniquely distorted. Further, variation of probe forces resulting from variations in substrate surface height gives rise to stresses that can fracture the substrate.
Despite the difficulties associated with single application, multi-element contacting, apparatus has been developed for testing complex electrical substrates such as MLC in this fashion. Particularly, U.S. Pat. No. 4,518,910, issued to Hottenrott et al., on May 21, 1985, assigned to the assignee of this application, describes apparatus capable of electrically testing MLC substrates in a single step.
The apparatus disclosed features contactors for electrically coupling the testing means to the substrate chip and I/O surfaces. The contactors each include a probe assembly having a plurality of spatially confined, electrically conductive probes designed to register with the entire metalization pattern of the respective substrate surface. The probes are further designed to accommodate any unevenness in the substrate surface height. Additionally, each contactor includes a probe space transformer comprising a plurality of wire fan-out elements connected to the probes for spatially expanding the probe pattern and electrically coupling the probes to the testing means.
The contactor for the substrate chip surface typically includes a probe assembly having a plurality of so called "buckling beam" probes. The electrically conductive beams have an axial length substantially greater than their cross section, and are arranged perpendicularly to the substrate surface. In this configuration, one end of each probe is fixed in the assembly housing, and the other is free and registered with the point in the metalization to be contacted.
When the probes are brought against the substrate, the engaging force at each increases as a function of substrate height. As the array is pressed against the substrate to insure complete contact, forces at each probe increase until the probe buckles. Once buckled, the probe engaging force remains substantially constant as the probe array is, thereafter, pressed to the substrate. This operation permits the forces applied by the contactor to remain substantially uniform across the substrate, even though the substrate height may vary significantly. A more detailed explanation of buckling beam probes and operation may be found in U.S. Pat. No. 3,806,801, issued Apr. 23, 1974, to R. Bove, and assigned to the assignee of this application.
The contactor for the substrate I/O surface, although not discussed in the noted patents, in the past has been required to use "pogo" probes. To properly test MLC, the substrate must be contacted at its chip and I/O surfaces simultaneously. But, as noted above, the MLC chip surface has many times more points to engage than the I/O surface. As a result, the force applied at the chip surface would be substantially greater than the force applied at the I/O surface if like type probe assemblies were used. Thus, to avoid a substantial imbalance in the applied forces which could lead to fracture of the substrate, it was necessary that the I/O probe assembly exert an engagement force in excess of what a conventional buckling beam assembly would be capable of. As a result, pogo probes, which have a wider range of engaging forces were selected for use at the substrate I/O surface contactor.
Each pogo probe includes an electrically conductive contact plunger that is spring loaded and slidably received in a conductive sleeve Selection of the sleeve spring controls the engaging force characteristic for the probe. The sleeves are fixedly mounted in the assembly housing. In operation, as the contactor is pressed against the substrate, the probe assembly plungers are pushed into their respective sleeves, compressing their associated springs. As the contactor is withdrawn, the respective springs restore the plungers to their original heights.
To electrically couple the spatially confined probes to the testing means, both the chip and the I/O contactors include a space transformer having a plurality of fan-out wire elements. The fan-out elements are simply collected in bundles of conveniently size to form cables which spatially expand and electrically connect the probes to the testing means. Adequate slack is provided in the cabling to permit free movement of the contactors during test.
While these contactors have enabled the MLC to be successfully tested, still a number of problems remain.
Particularly, in operation, the I/O contactor is repeatedly moved to and from the substrate to "sandwich" the substrate between the chip surface contactor and the I/O contactor for test. As a result of this repeated movement, the fan-out wires, especially those of the I/O space transformer, are subject to work hardening and breakage. But, once a fan-out wire breaks, locating it for repair among all the other fan-out wires requires many man-hours. The consequence is that where failure occurs, repair becomes commercially impractical. And, since the fan-out elements are fixed to the probe assembly, it may be necessary to discard the entire contactor and replace it with a new one; i.e., probe assembly and fan-out elements. As can be appreciated, this is costly and, therefore, undesirable.
Additionally, both the buckling beam probes and the pogo probes are also subject to failure. While the buckling beam probes are simpler and more reliable than pogo probes, the buckling beam probes can, nonetheless, experience difficulty. Buckling beam probes are typically small; e.g., 5 mils in diameter, and lightweight. In operation, their substrate engaging ends can become bent and deformed rendering them inoperative or, worse, a source of damage to the substrate. Since the probes are small and fixed in the contactor, their repair or replacement is impractical. Accordingly, replacement of the probe assembly, or some part of it, along with the respective fan-out elements is required. The result is substantial and undesirable replacement costs.
The pogo probes, because of their mechanical complexity, are even more susceptible to failure. Wear and dirt arising from relative movement of the plunger and sleeve can reduce probe conductivity. Further, the spring can cause the plunger to be ejected from the sleeve following test, rendering the probe inoperative. And, failure of the spring can cause the plunger to be impotently depressed within the sleeve, unable to contact the substrate. Again, because the probes are fixed in the contactor, their repair becomes commercially impractical. The result, once more, is undesirable replacement costs.
A further drawback of the pogo contactor is its inability to maintain uniform engaging force when used on substrates of nonuniform height. Spring loading of the plungers causes engaging force to continually increase as the probes are urged against the substrate. Where substrate height is nonuniform, nonuniform probe forces arise that can cause substrate damage.
Additionally, neither the buckling beam probe contactor, nor the pogo contactor include means for moving the probe assembly in the plane of the substrate metalization for alignment purposes. Typically, an adjustment of the relative position between the substrate and probes is effected by moving the substrate. However, such an arrangement does not allow for relative movement of the probe assemblies, and, therefore, prevents independent alignment of the chip surface probe assembly and the I/O probe assembly with the substrate. While probe displacement means have been proposed; for example, in U.S. Pat. No. 4,063,172, issued to Faure et al. and assigned to the assignee of this application, they are manually operated and require a complicated drive mechanism which is unsuited for automatic and simple repositioning of the probes.
A still further problem is that contactor failures not only add equipment replacement costs, but also, increase testing time and expense. Because so many things can go wrong in contacting the MLC; e.g., fan-out element breakage, probe damage resulting in improper probe alignment or inadequate engagement of the metalization, initial indications of MLC defect generated by the testing means must be verified before they can be considered actual. Accordingly, additional test steps, with their associated time and expense, are required to verify that a fault indication is truly due to a substrate defect, and not a contactor failure.
In the past, substrate test methods included verification steps that required successive tests at several testing units. Following a first substrate test at the primary test apparatus, a second test was undertaken at the primary apparatus in which the relative position of the substrate and probe assembly was adjusted. By adjusting relative position, the substrate metalization points in the second test were associated with probe elements different from those the metalization points were associated with in the first test. This adjustment of contact points and associated probe elements permitted identification of at least some of the spurious fault indications attributable to substrate contacting problems.
Where, based on the tests at the primary apparatus, substrate fault indications were considered likely to be valid, the substrate was removed to a secondary apparatus and tested yet again. The secondary test apparatus was equipped with probe assemblies having a few precisely locatable probe elements that could reliably retest the MLC circuits indicated as defective, thereby, eliminating any question of whether the fault indication was attributable to contacting problems If the secondary apparatus also showed the defect, the defect was considered confirmed, and steps taken to compensate it. Accordingly, by identifying and eliminating at least some of the spurious fault indications at the primary apparatus, testing at the secondary apparatus, and with it overall test time and expense, was reduced.
However, since retest of the substrate at the primary test apparatus required rotation of the substrate about an axis of symmetry common to both the substrate chip and I/O metalization patterns, retest could not be carried out were one, or the other, or both patterns were asymmetrical. As a result all fault verification in substrates having asymmetrical metalization patterns were required to be done at the secondary test apparatus. Where the number of defect indications at the primary apparatus is high, however, verification at the secondary apparatus becomes excessively time consuming and expensive. Further, that time and expense is unjustified, from a product standpoint, where fault indications are due to contactor problems, and not substrate defects. Therefore it would be most desirable to improve substrate test methods so that both substrates having symmetrical as well as asymmetrical metalization patterns could be retested at the primary test apparatus.